International Journal of Advanced Education and Research

International Journal of Advanced Education and Research


International Journal of Advanced Education and Research
International Journal of Advanced Education and Research
Vol. 1, Issue 3 (2016)

FFT implementation with fused floating-point operations


Mr. A. Ramakrishna, B. Kavya, K. Ganesh, N. Gayathri, P. Ramya Sudha, D. Satish

This paper describes two fused floating-point operations and applies them to the implementation of fast Fourier transform (FFT) processors. The fused operations are a two-term dot product and an add-subtract unit. The FFT processors use “butterfly” operations that consist of multiplications, additions, and subtractions of complex valued data. Both radix-2 and radix-4 butterflies are implemented efficiently with the two fused floating-point operations. When placed and routed using a high performance standard cell technology, the fused FFT butterflies are about 15 percent faster and 30 percent smaller than a conventional implementation. Also the numerical results of the fused implementations are slightly more accurate, since they use fewer rounding operations. Index Terms—Floating-point arithmetic, fused floating-point operations, fast Fourier transform, Radix-2 FFT butterfly, Radix-4 FFT butterfly.
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